Flash and other types of electronic memory devices are constructed of memory cells that individually store and provide access to data. A first generation type memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells, where the data can then be retrieved in a read operation. In addition to programming (sometimes referred to as write) and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is set to a known initial state (e.g., a one “1”).
The individual memory cells typically comprise a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device in which a binary piece of information may be retained. The erase, program, and read operations are commonly performed by application of appropriate voltages to specific terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in or removed from the memory cell. In a read operation, appropriate voltages are applied to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed.
Flash memory is a non-volatile type of memory which can be modified and hold its content without power. Conventional single-bit flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. Each such flash memory cell includes a transistor structure having a source, a drain, and a channel in a substrate or doped well, as well as a gate storage structure overlying the channel. The gate storage structure may include dielectric layers formed on the surface of the doped well. The dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer.
A new generation of non-volatile memory that has emerged is called resistance changing memory, wherein a variable resistance is employed to identify a state of a memory cell. Such resistance changing memory devices have some advantages in reducing cell size and therefore improving memory cell density, thereby reducing memory cost.
One exemplary prior art resistance changing memory unit cell is illustrated in prior art FIG. 1, at reference numeral 10. In FIG. 1, the unit cell 10 comprises a resistance changing memory element 12 coupled between a bit line 14 and a select transistor 16. The select transistor 16 has a gate terminal 18 coupled to a word line 20, and is coupled between the memory element 12 and a common source potential 22 such as ground. The unit cell 10 of prior art FIG. 1 is configured in what some call a NOR type array architecture. In the NOR architecture, multiple unit cells 10 are coupled as illustrated along a single bit line 14, and coupled to ground. In addition, multiple bit lines or columns are provided, and word lines 20 or rows extend substantially perpendicular thereto. Extending word lines 20 couple to respective unit cells of differing bit lines. In the above manner, multiple cells may be addressed concurrently, wherein by addressing a single word line, those unit cells of different bit lines coupled to the addressed word line are addressed. This concurrent addressing is sometimes referred to as a page mode.
An exemplary cross section of a resistance changing unit cell 10 is illustrated in prior art FIG. 2. The unit cell comprises the select transistor 16 having a gate electrode 18 coupled to the word line 20 (not shown). The transistor 16 has source and drain regions, wherein the source region 24 is coupled to a common source potential 22, and the drain 26 is coupled to the resistance changing element 12 via conductive contacts 28. The resistance changing element 12 is then coupled to an overlying bit line 14 via another conductive contact 30. The above layout is relatively compact and advantageously provides a relatively high density non-volatile memory architecture.
It is always desirable to provide further improvements in non-volatile memory technology.